Digital Phase-Locked Loop (Dpll); Clock Usage Method - Samsung S3C2500B User Manual

S3C2500B

8.4.8 DIGITAL PHASE-LOCKED LOOP (DPLL)

The HDLC module contains a digital phase-locked loop (DPLL) function to recover clock information from a data
stream with NRZI or FM encoding. The DPLL is driven by a clock that is normally 32 (NRZI) or 16 (FM) times the
data rate. The DPLL uses this clock, along with the data stream, to construct the clock.
This clock may then be used as the receive clock, the transmit clock, or both.
Figure 8-3 shows a block diagram of the digital phase-locked loop. It consists of a 5-bit counter, an edge detector
and a pair of output decoders.
RxD
Edge
Detector
TxC
RxC
MCLK2
BRGOUT1
BRGOUT2
HMODE[18:16]

8.4.9 CLOCK USAGE METHOD

BRGCLK
RxC
MCLK2
TxCLK
TxC
RxC
DPLLOUTT
BRGOUT1
BRGOUT2
NOTE: BRGCLK = HMODE [19]
DPLLCLK = HMODE [18:16]
TxCLK = HMODE [22:20]
RxCLK = HMODE [26:24]
Count Modifier
5-bit Counter
Figure 8-3. DPLL Block Diagram
BRGOUT1
Baud Rate
Generator
BRGOUT2
Transmit Transmit
Transmitter
Clock Data
Figure 8-4. Clock Usage Method Diagram
Receive Clock
Decoder
Transmit clock
Decoder
DPLLCLK
TxC
RxC
MCLK2
BRGOUT1
BRGOUT2
RxCLK
TxC
RxC
Receive
DPLLOUTR
Clock
BRGOUT1
BRGOUT2
HDLC CONTROLLER
dplloutR
dplloutT
DPLLOUTT
DPLL
DPLLORTR
Receive
Receiver
Data
8-9