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S3C2500B
8.3 FUNCTION DESCRIPTIONS
Figure 8-1 shows the HDLC module's function blocks. These function blocks are described in detail in the
following sections.
Address
DMA
Controlller
Control
Bus Arbiter/
Data
Controller
Address
Tx FIFO
(8 Words)
Flag/Abort/Idle
Generateor and
Transmitter
HDLC Control
and Status
Registers
Word
FCS Checker
Receive shift
Register
Rx FIFO
(8 words)
Figure 8-1. HDLC Module Block Diagram
FCS Generator
Zero
Encoder
Insertion
Flag/Abort/Idle
Detection
Zero
Delection
Decoder
dplloutR
DPLL
dplloutT
brgout1
brgout2
HDLC CONTROLLER
autoecho
TxD
loop
RxD
TxC
RxC
BRG
MCLK2
(= 66 MHz)
8-3
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