Samsung S3C2500B User Manual page 332

ETHERNET CONTROLLER
7.4.1.10 BDMA/MAC Receive Interrupt Status Register
Registers Address
BMRXSTATA 0xF00A0024
BMRXSTATB 0xF00C0024
Table 7-23. BDMA/MAC Receive Interrupt Status Register Description
Bit Number
[0] Missed roll (MissRoll)
[1] Alignment error (AlignErr)
[2] CRC error (CRCErr)
[3] Overflow error (Overflow)
[4] Long error (LongErr)
[5] Parity error (RxParErr)
[6]
[15:7] Reserved
[16] BDMA Rx done in every
received frames (BRxDone)
[17] BDMA Rx not owner (BRxNO)
[18] BDMA Rx maximum size over
(BRxMSO)
[19] BDMA RxBUFF Full (BRxFull)
[20] Early notification (BRxEarly)
[21] One more frame data in BDMA
RxBUFF (BRxFRF), read-only
[26:22] Number of frames in BRxBUFF
(BRxNFR), read-only
[31:27] Reserved
7-22
Table 7-22. BMRXSTAT Register
R/W
R/W
R/W
Bit Name
This bit is set when the missed error counter rolls over.
Whenever this bit is set, the MISSCNT register should be read
to clear this bit. Writing by ARM doesn't affect the Rx interrupt.
This bit is set if the frame length in bits is not a multiple of
eight and the CRC is invalid. For the MAC Rx control mode of
MIgnoreCRC, this bit is not set.
This bit is set if the CRC at the end of frame did not match the
computed value, or else the PHY asserted RX_ER during
frame reception.
This bit is set if the MAC RxFIFO was full when it needed to
store a received byte.
This bit is set if the MAC received a frame longer than 1518
bytes. (It is not set if the long enable bit in the receive control
register, MACRXCON, is set.)
This bit is set if a parity error is detected in the MAC RxFIFO.
– Factorial test bit
Not applicable.
This bit is set each time the BDMA receiver moves one
received data frame to memory. This bit must be cleared for
the next frame interrupt generation.
This bit is set when BDMA is not the owner and the reception
process is stop.
This bit is set when the value of received frame size is larger
than one of the Rx frame maximum size.
This bit is set when the BDMA RxBUFF is in the full-flag state.
This bit is set when the BDMA moves the Length/Ether-type
field of the current frame to the external memory.
This bit is set whenever an additional data frame is received in
the BDMA receive buffer.
These bits appear number of frames in BRxBUFF.
Not applicable
Description
BDMA/MAC Rx Interrupt Status register
BDMA/MAC Rx Interrupt Status register
Description
S3C2500B
Reset Value
0x00000000
0x00000000