Samsung S3C2500B User Manual page 517

GDMA CONTROLLER
Bit Number
Transfer size
[7:6]
[9:8] Source address direction These bits control whether the source address will be increased
[11:10] Destination address
direction
Interrupt enable
[12]
[16:13] External GDMA ACK
count
[31] Busy status
NOTE: To ensure the reliability of GDMA operations, the GDMA control register bits must be configured independently and
carefully. If you want four-bust-mode (DCON[5]), you should set both SD (DCON[9:8]) and DD (DCON[11:10]) to
"00" (increase). But SD (DCON[9:8]) and DD (DCON[11:10]) can be "10" (fixed) only for USB endpoints (software
mode) and DES IN/OUT FIFO (DES mode) when four-burst-mode (DCON[5]) is set.
12-10
Table 12-4. GDMA Control Register Description (Continued)
Bit Name
These bits determine the transfer data width to be one byte, one
half-word, or one word. If you select a byte transfer operation, the
source/destination address will be increased or decreased by one
with each transfer. Each half-word transfer increments or
decrements the address by two, and each word transfer by four.
NOTE:
("00"), decreased ("01"), or fixed ("10") during a GDMA operation.
The "fixed" ("10") means the source address will not be changed
during a GDMA operation. You use this "fixed" feature when
transferring data from a single source to multiple destinations.
When DCON MODE [3:1] is HUART RX mode (HUART to memory,
"011") or DES OUT mode (DES to memory, "101"), these bits don't
care.
These bits control whether the destination address will be increased
("00"), decreased ("01"), or fixed ("10") during a GDMA operation.
The "fixed" ("10") means the destination address will not be
changed during a GDMA operation. You use this "fixed" feature
when transferring data from multiple sources to a single destination.
When DCON MODE [3:1] is HUART TX mode (HUART from
memory, "010") or DES IN mode (DES from memory, "100"), these
bits don't care.
If the interrupt enable bit is "1", a GDMA interrupt is generated when
GDMA operation completes successfully. If this bit is "0", the GDMA
interrupt is not generated. If you stop the GDMA operation by
resetting the run enable bit, the GDMA interrupt is not generated
regardless of this bit.
These bits control how many cycles of the external GDMA
acknowledgement signals provided. If the slow external devices
want GDMA service, the slow external devices can sample the
external GDMA ACK signal by setting these bits. These bits provide
the range of 1 and 16 cycles. If these bits are "0000", the single
cycle of the external GDMA ACK are generated. If these bits are
"1111", the 16 cycles of the external GDMA ACK are generated.
When GDMA starts, this read-only status bit is automatically set to
"1". When it is "0", GDMA is idle. This bit is a read-only bit.
Description
In HUART mode, you should set byte ("00") on transfer size
(TS) [7:6] of DCON register. In DES mode, you should set word
("10") on transfer size (TS) [7:6] of DCON register.
S3C2500B