MEMORY CONTROLLER
HCLKO
nRCS
nSDWE
tADDRd
ADDR
DATA
5-30
tRCSd
tnSDWEd
tDATAd
TACC = 0x8 (8 cycles)
TCOH = 0x0 (0 cycle)
Figure 5-15. Write Timing Diagram 1
tACC
tnSDWEh
Addr
Data
TCOS = 0x0 (0 cycle)
TACS = 0x0 (0 cycle)
tRCSh
tADDRh
tDATAh
S3C2500B
