HDLC CONTROLLER
TxClock
TxD
RTS
CTS
If nCTS remains still High for a while after nRTS enters Low to allow data transmission from HTxFIFO, the data
transmission starts 5-12 cycles after nCTS is shifted to Low
8-18
5 - 12 cycles
Figure 8-9. CTS Delayed on
S3C2500B
Data