Samsung S3C2500B User Manual page 398

HDLC CONTROLLER
Bit Bit Name
Number
[11] Rx flag detected (RxFD)
[12] Rx data carrier detected
(RxDCD)
[13] Rx stored data carrier
detected (RxSDCD)
[14] Rx frame valid (RxFV)
[15] Rx idle (RxIDLE)
[16] Rx abort (RxABT)
[17] Rx CRC error (RxCRCE) The RxCRCE status bit is set a frame is completed with a CRC error.
[18] Rx non-octet align
(RxNO)
[19] Rx overrun (RxOV)
[20] Reserved
[21] Reserved.
[22] DMA Tx abort
(DTxABT)
8-38
Table 8-12. HSTAT Register Description (Continued)
This bit is set to '1' when the last bit of the flag sequence is received. This
bit generates an interrupt if enabled. You can clear this bit by writing a '1'
to this bit.
The DCD status bit mirrors the state of the nDCD input pin. If nDCD input
pin is low, this status bit is '1'. If nDCD input pin is High, it is '0'. This bit
does not generate an interrupt.
This bit is set to '1' when a transition in nDCD input occurs, and can
generate interrupt, if enabled. You can clear this bit by writing a '1' to this
bit.
This bit signals frame's ending boundary to the CPU and also indicates
that no frame error occurred. It is set when the last data byte of a frame is
transferred into the last location of the Rx FIFO and is available to be
read.
The RxIDLE status bit indicates that a minimum of 15 consecutive 1s
have been received. The event is stored in the status register and can be
used to trigger a receiver interrupt. The RxIDLE bit continues to reflect
the inactive idle condition until a '0' is received. You can clear this bit by
writing a '1' to this bit.
The RxABT status bit is set to '1' when seven or more consecutive 1s
(abort sequence) have been received. When an abort is received in an
'in-frame' condition, the event is stored in the status register triggering an
interrupt request. You can clear this bit by writing a '1' to this bit.
The RxNO bit is set to '1', if received data is non-octet aligned frame.
The RxOV status bit is set to '1', if the data received is transferred into
the HRXFIFO when it is full, resulting in a loss of data. Continued
overruns destroy data in the first FIFO register.
Not applicable.
Not applicable.
This bit is set to '1' when abort signal is sent due to the Tx underrun or
CTS lost occurred. If this bit is set, DTxEN(in HCON) bit cleared. You can
clear this bit by writing '1' to this bit.
Description
S3C2500B