Samsung S3C2500B User Manual page 389

S3C2500B
31 30 28 27 26
TXC
RxCLK
OPS
[0] Muilt-Frame in TxFIFO in DMA Operation (MFF)
0 = Single frame in TxFIFO
1 = Multi frame in TxFIFO
[1] Reserved
[2] Rx Clock Inversion (RxCINV)
0 = Rx clock rising
[3] Tx Clock Inversion (TxCINV)
0 = Tx clock falling
[4] Rx Little-Endian Mode (RxLittle)
0 = The Rx data on the system bus is in Big-Endian format.
1 = The Rx data on the system bus is in Little-Endian format.
[5] Tx Little-Endian Mode (TxLittle)
0 = The Tx data on the system bus is in Big-Endian format.
1 = The Tx data on the system bus is in Little-Endian format.
[6] Rx Transparent Mode (RxTRANS)
0 = The Rx operates HDLC mode
1 = The Rx operates transparent mode
[7] Tx Transparent Mode (TxTRANS)
0 = The Tx operates HDLC mode
1 = The Tx operates transparent mode
[10:8] Tx Preamble Length (TxPL)
000 = 1 byte
001 = 2 byte
010 = 3 byte
011 = 4 byte
[11] Reserved
[14:12] Data Format (DF)
000 = NRZ data format
010 = FM0
100 = Manchester
24 23 22 20 19 18
B
R
G DPLL
TxCLK
C CLK
L
K
1 = Rx clock falling
1 = Tx clock rising
100 = 5 byte
101 = 6 byte
110 = 7 byte
111 = 8 byte
001 = NRZI
001 = FMI
Figure 8-13. HMODE Register
16 15 14 12 11 10
R
T
R
n
DF TxPL
R
T
S
[15] RTRnRTS
0 = Request to send
1 = Receive to ready
[18:16] DPLL Clock Select (DPLLCLK)
000 = TXC pin
010 = MCLK2
100 = BRGOUT2
[19] BRG Clock Select (BRGCLK)
0 = RXC pin is selected.
1 = MCLK2 is selected.
[22:20] Tx Clock Select (TxCLK)
000 = TXC pin
010 = DPLLOUTT
100 = BRGOUT2
[26:24] Rx Clock Select (RxCLK)
000 = TXC pin
010 = DPLLOUTT
100 = BRGOUT2
[27] Reserved
[30:28] TXC Output Pin Select (TXCOPS)
This pin is used for output only when it is not used as
an input clock for the DPLL, TxCLK, or RxCLK.
000 = Tx Clock
010 = BRGOUT1
100 = DPLLOUTT
[31] Reserved
HDLC CONTROLLER
8 7 6 5 4 3 2 1
T R
T R
x x T R
x x
L L x x
T T
i i C C
R R
t
t I I
A A
t t N N
N N
l
l V V
S S
e
e
001 = RXC pin
011 = BRGOUT1
001 = RXC pin
011 = BRGOUT1
001 = RXC pin
011 = BRGOUT1
001 = Rx Clock
011 = BRGOUT2
101 = DPLLOUTR
0
M
F
F
8-29