Samsung S3C2500B User Manual page 55

S3C2500B
Group Pin Name
Ethernet RX_ERR_0
Controller0
(18)
Ethernet MDC_1
Controller1
(18)
MDIO_1
COL_1
TX_CLK_1
Table 1-1. S3C2500B Signal Descriptions (Continue)
Pin Type Pad Type
1 I
1 O
1 I/O
1 I
1 I
phisd Receive Error.
PHY asserts RX_ERR synchronously
whenever it detects a physical medium error
(e.g., a coding violation). PHY asserts
RX_ERR only when it asserts RX_DV.
phob12 Management Data Clock.
The signal level at the MDC pin is used as a
timing reference for data transfers that are
controlled by the MDIO signal.
phbcut12 Management Data I/O.
When a read command is being executed,
data that is clocked out of the PHY is
presented on this pin. When a write command
is being executed, data that is clocked out of
the controller is presented on this pin for the
Physical Layer Entity, PHY.
phis Collision Detected/Collision Detected for 10M.
COL is asserted asynchronously with
minimum delay from the start of a collision on
the medium in MII mode. COL_10M is
asserted when a 10-Mbit/s PHY detects a
collision.
phis Transmit Clock/Transmit Clock for 10M.
The controller drives TXD[3:0] and TX_EN
from the rising edge of TX_CLK. In MII mode,
the PHY samples TXD[3:0] and TX_EN on the
rising edge of TX_CLK. For data transfers,
TXCLK_10M is provided by the 10M-bit/s
PHY.
PRODUCT OVERVIEW
Description
1-21