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S3C2500B
HDLC CONTROLLER
8
HDLC CONTROLLER
8.1 OVERVIEW
The S3C2500B has three high-level data link controllers (HDLCs) to support three-channel serial communica-
tions.
The HDLC module supports a CPU/data link interface that conforms to the synchronous data link control (SDLC)
and high-level data link control (HDLC) standards. In addition, the following function blocks are integrated into the
HDLC module:
— Three-channel DMA engine for Tx/Rx
— Support buffer descriptors per frame
— Digital phase-locked loop (DPLL) block
— Baud rate generator (BRG)
8-1
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