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Figure
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List of Figures
HDLC Module Block Diagram ................................................................................ 8-3
Baud Rate Generator Block Diagram..................................................................... 8-7
DPLL Block Diagram ............................................................................................. 8-9
Clock Usage Method Diagram ............................................................................... 8-9
Data Encoding Methods and Timing Diagrams ...................................................... 8-12
HDLC Data Setup and Timing Diagrams................................................................ 8-13
nCTS Already Asserted ......................................................................................... 8-17
CTS Lost During Transmission .............................................................................. 8-17
CTS Delayed on .................................................................................................... 8-18
Transmit Buffer Descriptor..................................................................................... 8-21
Receive Buffer Descriptor...................................................................................... 8-22
Data Structure of the Receive Data Buffer............................................................. 8-23
HMODE Register................................................................................................... 8-29
HDLC Control Register .......................................................................................... 8-34
HDLC Status Register............................................................................................ 8-40
HDLC Interrupt Enable Register............................................................................. 8-43
HDLC Tx FIFO Function Diagram.......................................................................... 8-44
HDLC Rx FIFO Function Diagram ......................................................................... 8-45
HDLC BRG Time Constant Register ...................................................................... 8-46
HDLC Preamble Constant Register........................................................................ 8-47
Address Recognition.............................................................................................. 8-48
HDLC Station Address and HMASK Register......................................................... 8-49
DMA Tx Buffer Descriptor Pointer.......................................................................... 8-49
DMA Rx Buffer Descriptor Pointer ......................................................................... 8-50
Maximum Frame Length Register.......................................................................... 8-50
DMA Receive Buffer Size Register ........................................................................ 8-51
HDLC Synchronization Register............................................................................. 8-51
Data Sampling Method .......................................................................................... 8-52
IOM2 Channel Structure in Terminal...................................................................... 9-2
Monitor Channel Handshake Protocol.................................................................... 9-4
Abortion of Monitor Channel Transmission ............................................................ 9-5
Structure of Last Byte of Channel 2 on DU ............................................................ 9-7
Structure of Last Byte of Channel 2 on DD ............................................................ 9-8
TSA Block Diagram ............................................................................................... 9-9
IOM2 Control Register ........................................................................................... 9-13
IOM2 Status Register ............................................................................................ 9-15
IOM2 Interrupt Enable Register ............................................................................. 9-17
IOM2 TIC Bus Address Register ............................................................................ 9-18
IOM2 IC Channel Transmit Data Register.............................................................. 9-19
IOM2 IC Channel Receive Data Register............................................................... 9-19
(Continued)
Title
S3C2500B RISC MICROCONTROLLER
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