Samsung S3C2500B User Manual page 224

SYSTEM CONFIGURATION
Each PLL can also be programmed by S/W register setting. Each PLL is in pin configurable mode after the
system reset is released. You can change the PLL configuration mode to the register configurable mode by set
CPLLREN, SPLLREN, UPLLREN, PPLLREN in the SYSCFG[31:28]. If the PLL register enable bit is set to "1,
the PLL multiplication factor is not from the external pin but from the corresponding PLLCON regiseter-
CPLLCON, SPLLCON, UPLLCON, PPLLCON registers. The PLL is controlled by the 3 control variables, P, M ,S.
When the PLL is under the control of the S/W and the PLL control variables are dynamically changed by the
S/W, the glitch may occur in the PLL output clock. You can avoid the glitch generation by set the PLL clock
enable bit, CPLLCE, SPLLCE, UPLLCE, PPLLCE in the SYSCFG [27:24]. When the PLL clock enable bit is set
to "0" during the PLL control variable change, the stable PLL output clock is provided. The PLL output frequency
is determined as follows.
Fout = Fin × (M+8) / ((P+2) × (2^S))
Where the Fin is the frequency of the PLL input clock and the Fout is the frequency of the PLL output clock.
The four PLLs in the S3C2500B are controlled by above formula and the table 4-4 shows the PLL variables for
the most widely used frequencies.
P[5:0]
00_0001
00_0001
00_0001
00_0001
00_0001
00_0001
00_0001
00_0001
00_0001
00_0001
00_0001
00_0011
00_0001
4-12
Table 4-4. P, M, S values of the S3C2500B PLL
M[7:0]
0101_0010
0100_1000
1000_0100
0111_0000
0101_1100
0101_0010
0100_1000
0100_0011
0111_0000
0100_1000
0111_0000
1011_1000
0100_1000
S[1:0] PLL Input Clock
Frequency
00
00
01
01
01
01
01
01
10
10
11
11
11
PLL Output Clock
Frequency
10MHz 300MHz
10MHz 266MHz
10MHz 233MHz
10MHz 200MHz
10MHz 166MHz
10MHz 150MHz
10MHz 133MHz
10MHz 125MHz
10MHz 100MHz
10MHz
10MHz
10MHz
10MHz
S3C2500B
66MHz
50MHz
48MHz
33MHz