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S3C2500B
Bit Number
Bit Name
[27]
Data END
(DEND)
[28]
SETup END
(SETEND)
[29]
SenD STALL
(SDSTALL)
[30]
SerViced Out
ReaDY
(SVORDY)
[31]
SerViced SETup
end
(SVSET)
Table 10-16. USBEP0CSR Register Description (Continued)
MCU
R/S
R
S
W
W
USB
C
The MCU sets this bit:
1. After loading the last packet of data into the
FIFO, at the same time INRDY is set.
2. While it clears ORDY after unloading the last
packet of data.
3. For a zero length data phase, when it clears
ORDY and sets INRDY.
S
This is a read only bit
The USB sets this bit when a control transfer ends
before DEND is set.
The MCU clears this bit by writing a 1 to the SVSET
bit.
When the USB sets this bit, an interrupt is
generated to the MCU.
When such a condition occurs, the USB flushes the
FIFO, and invalidates MCU access to the FIFO.
When MCU access to the FIFO is invalidated, this
bit is cleared.
Clear
The MCU writes a 1 to this bit at the same time it
clears ORDY, if it decodes a invalid token.
The USB issues a STALL handshake to the current
control transfer.
The MCU writes a 0 to end the STALL condition.
Clear
The MCU writes a 1 to this bit to clear ORDY
Clear
The MCU writes a 1 to this bit to clear SETEND
USB CONTROLLER
Description
10-23
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