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IOM2 CONTROLLER
S3C2500B
The availability of the S/T interface D-channel is indicated in bit5 "Stop/Go" of the DD last byte of channel2
(Figure 9-5).
S/G
A/B
Available/Blocked
Stop/Go
Figure 9-5. Structure of Last Byte of Channel 2 on DD
The IOM2 controller checks the S/G bit to determine if the D channel is available to access. If the D channel is
available (S/G=0), an HDLC frame is transmitted. If the D channel is busy with other device, the IOM2 controller
should halt the transmission. Bits 7 and 6 are the D channel Echo bits from the S-interface (echo back the two D
channel bits of the current frame) and are used to determine D channel collisions. The echo bits are compared
with the sent D channel bits to determine if a collision has occurred. The IOM2 controller does not support the
A/B bit.
9.3.7.6 IC Channel Operation
The IOM2 controller can have access to two IC channels by reading the IOM2ICRD and writing the IOM2ICTD
register. Only one channel must be accessed at a time since the IOM2 controller has registers for one channel.
The IC channel0 is accessed by setting the ICSEL bit to "0". Because the data output is open-drain, the unused
IC channel and all High bits of the chosen IC channel are placed in a high-impedance state (unless used by an
HDLC frame).
9.3.7.7 Pin Direction Reversal
The data signals on the IOM2 bus are defined as Data Upstream (DU) and Data Downstream (DD). In terminal
mode, a device may be required to transmit both upstream and downstream, based on which channel is being
transmitted at any one time. As a result, the actual data pins of the S3C2500B IOM2 interface need to be both
inputs and outputs. When the DBREV bit in IOM2CON is set, the DU pin is used to receive downstream data and
the DD pin is used to send upstream data.
9.3.7.8 Strobe Signals
The optional IOM2 signals, BCL and STRB, are used by non-IOM2 devices on the IOM2 bus. BCL is a 1x clock
running at 768 kHz and used as the data clock. STRB is used to specify a strobe of an appropriate time slot for
non-IOM2 device. The start and stop position of STRB is programmed by IOM2STRB register
9-8
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