Samsung S3C2500B User Manual page 248

MEMORY CONTROLLER
Table 5-13 and 5-14.
Using little-endian and byte access, Program/Data path between register and external memory.
WA=Address whose LSB is 0, 4, 8, C, EA=External Address
HA=Address whose LSB is 0, 2, 4, 6, 8, A, C, E
BA=Address whose LSB is 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F
X=Don't care.
Table 5-13. External 8-bit Datawidth Store Operation with Little-Endian
Transfer Width
Bit Num.
CPU Register Data
CPU Address
Bit Num.
CPU Data Bus
External Address (ADDR)
Bit Num.
External Data
Timing Sequence
Table 5-14. External 8-bit Datawidth Load Operation with Little-Endian
Transfer Width
Bit Num.
CPU Register Data
CPU Address
Bit Num.
CPU Data Bus
External Address (ADDR)
Bit Num.
External Data
Timing Sequence
5-12
STORE (CPU Reg → → External Memory)
32-bit
31 0
abcd
WA
31 0
abcd
EA+3 EA+2
7 0 7 0
a b
1st 2nd
LOAD (CPU Reg ← ← External Memory)
32-bit
31 0
abcd
WA
31 0 31 0
axxxx abxx
EA+3 EA+2
7 0 7 0
a b
1st 2nd
EA+1 EA
7 0 7 0
c d
3rd 4th
31 0 31 0
abcx abcd
EA+1 EA
7 0 7 0
c d
3rd 4th
S3C2500B
16-bit
31 0
xxab
HA
31 0
abab
EA+1 EA
7 0 7 0
a b
1st 2nd
16-bit
31 0
xxab
HA
31 0 31 0
axax abab
EA+1 EA
7 0 7 0
a b
1st 2nd
8-bit
31 0
xxxa
BA
31 0
aaaa
EA
7 0
a
8-bit
31 0
xxxa
BA
31 0
aaaa
EA
7 0
a