Table of Contents
Advertisement
S3C2500B
31
30
29
EXTMASK
G
[6:0] Individual external interrupt mask bits
NOTE:
[31] Global interrupt mask bit
28
27
26
25
24
23
22
21
Each of the 7 bits in the external interrupt mask register, EXTMASK,
(except for the global mask bit, G) corresponds to an external interrupt source.
When a source interrupt mask bit is 1, the interrupt is not serviced by the
ARM940T when the corresponding interrupt request is generated. If the mask
bit is 0, the interrupt is serviced upon request. And if global mask bit
(bit 31) is 1, no interrupts (include internal and external interrupts) are serviced.
After the global mask bit is cleared, the interrupt is serviced.
The 7 interrupt sources are mapped as follows:
[6] IOM2 interrupt
(0 = non-Masking, 1 = Masking)
[5] EXT 5 interrupt
[4] EXT 4 interrupt
[3] EXT 3 interrupt
[2] EXT 2 interrupt
[1] EXT 1 interrupt
[0] EXT 0 interrupt
0 = Enable all interrupt requests
Figure 16-4. External Interrupt Mask Register (EXTMASK)
14
13
20
19
18
17
16
15
1 = Disable all interrupt requests
INTERRUPT CONTROLLER
12
11
10
9
8
7
6
5
X
X
4
3
2
1
0
X
X
X
X
X
16-7
Advertisement
Table of Contents
