Samsung S3C2500B User Manual page 388

HDLC CONTROLLER
Bit Bit Name
Number
[14:12] Data formats (DF)
[15] RTR/RTS mode select
(RTRnRTS)
[18:16] DPLL clock select
(DPLLCLK)
[19] BRG clock select
(BRGCLK)
[22:20] Tx clock select (TxCLK)
[26:24] Rx clock select (RxCLK)
[30:28] TXC output pin select
(TXCOPS)
[31] Reserved
8-28
Table 8-8. HMODE Register Description (Continued)
When the DF bits are '000', data is transmitted and received in the NRZ
data format. When DF is '001', the NRZI (zero complement) data format
is selected. DF = '010' selects the FM0 data format, DF = '011' the FM1
data format, and DF = '100' the Manchester data format.
RTR, RTS mode select bit. When RTRnRTS is '0', the mode is
RTS(Request To Send), when RTRnRTS is '1', the mode is
RTR(Received To Ready).
Using this setting, you can configure the clock source for DPLL to one of
the following pins: TXC, RXC, MCLK2, BRGOUT1, or BRGOUT2. To
select one of these pins, set the DPLLCLK bits to '000', '001', '010', '011',
or '100', respectively.
If this bit is '1', MCLK2 is selected as the source clock for the baud rate
generator (BRG). If this bit is '0', the external clock at the RXC pin is
selected as the BRG source clock.
Using this setting, you can configure the transmit clock source to one of
the following pins: TXC, RXC, DPLLOUTT, BRGOUT1, or BRGOUT2.
To select one of these pins, set the TxCLK bits to '000', '001', '010', '011',
or '100', respectively.
Using this setting, you can configure the receive clock source to one of
the following pins: TXC, RXC, DPLLOUTR, BRGOUT1, or BRGOUT2.
To select one of these pins, set the RxCLK bits to '000', '001', '010', '011',
or '100', respectively.
If you do not use the clock at the TXC pin as the input clock(DPLLCLK,
TxCLK, RxCLK must not '000' ), you can use the TXC pin to monitor
TxCLK, RxCLK, BRGOUT1, BRGOUT2, DPLLOUTT, and DPLLOUTR.
To select the clock you want to monitory, set the TXCOPS to '000', '001',
'010', '011', or '100', '101' respectively.
Not applicable.
Description
S3C2500B