System Configuration Register - Samsung S3C2500B User Manual

SYSTEM CONFIGURATION
4.9.1 SYSTEM CONFIGURATION REGISTER (SYSCFG)
You can control the system bus arbitration method, PLL operation, system clock output enable/disable function,
external memory address remap function and Little/Big information read function by SYSCFG.
Register Address
SYSCFG 0xF0000000
SYSCFG Bit
CPLLREN [31]
SPLLREN [30]
UPLLREN [29]
PPLLREN [28]
CPLLFD [27]
SPLLFD [26]
4-16
R/W
R/W
CPLLCON register enable
This bit controls which value is used for the CPU PLL constant from
the two constant values. When this bit is set to "0", the CPU PLL
constant is from CPU_FREQ[2:0] setting. When this bit is set to "1",
the CPU PLL constant is from the CPLLCON register.
SPLLCON register enable
This bit controls which value is used for the BUS PLL constant from
the two constant values. When this bit is set to "0", the BUS PLL
constant is from BUS_FREQ[2:0] setting. When this bit is set to "1",
the BUS PLL constant is from the SPLLCON register.
UPLLCON register enable
This bit controls which value is used for the USB PLL constant from
the two constant values. When this bit is set to "0", the BUS PLL
constant is always set to generates the clock frequency 4.8 times
the input clock. When this bit is set to "1", the USB PLL constant is
from the UPLLCON register.
PPLLCON register enable
This bit controls which value is used for the PHY PLL constant from
the two constant values. When this bit is set to "0", the PHY PLL
constant is from PHY_FREQ setting. When this bit is set to "1", the
PHY PLL constant is from the PPLLCON register.
CPLL filter disable
This bit determines whether the CPU PLL output is filtered or not
during the configuration. When this bit is set to "0", the CPU PLL
output is filtered to be provided to the system during the
configuration. In this case, the glitch output from PLL can be
masked. When this bit is set to "1", the CPU PLL output is not
filtered to be provided to the system.
SPLL filter disable
This bit determines whether the BUS PLL output is filtered or not
during the configuration. When this bit is set to "0", the BUS PLL
output is filtered to be provided to the system during the
configuration. In this case, the glitch output from PLL can be
masked. When this bit is set to "1", the BUS PLL output is not
filtered to be provided to the system.
Description

System configuration register

Description
S3C2500B
Reset Value
–
Initial State
0
0
0
0
0
0