Bdma Relative Special Register - Samsung S3C2500B User Manual

S3C2500B

7.4.1 BDMA RELATIVE SPECIAL REGISTER

7.4.1.1 Buffered DMA Transmit Control Register
Registers Address
BDMATXCONA 0xF00A0000
BDMATXCONB 0xF00C0000
Bit Number
[3:0] BDMA Tx Number of Buffer
Descriptor (BTxNBD)
[6:4] BDMA transmit to MAC Tx
start level (BTxMSL)
[7] Tx Byte Swapping
(BTxBSWAP)
[8] Reserved
[9]
[10] BDMA Tx enable (BTxEn)
[11] BDMA Tx reset (BTxRS)
[31:12] Reserved
Table 7-4. BDMATXCON Register
R/W
R/W
R/W
Table 7-5. BDMA Transmit Control Register Description
Bit Name
You can select number of buffer descriptor.
0000 = 2
These bits determine when to move the data of the new frame in
the BDMA Tx Buffer (BTxBUFF) to the MAC TxFIFO (MTxFIFO)
at a new frame arrival.
000 means no wait, 001 means wait to fill 1/8 of the BDMA Tx
Buffer, 010 means wait to fill 2/8 of the buffer, and so on through
100, which means wait to fill 4/8 of the BDMA Tx Buffer.
NOTE:
Use to prevent disorder of byte sequence when memory operate
on big-endian format and byte unit access.
If this bit is set, the transferring byte is swapped.
(B3,B2,B1,B0) à (B0,B1,B2,B3)
Not applicable.
– Factorial test bit
When the Tx enable bit is set to '1', the BDMA Tx block is
enabled. Even if this bit is disabled, buffer data will be moved to
the MAC TxFIFO until the BDMA TxBUFF underflows.
This bit is automatically cleared when the BDMA is not the owner.
NOTE:
Set this bit to '1' to reset the BDMA Tx block.
Description
Buffered DMA transmit control register
Buffered DMA transmit control register
Description
0 1
, 0001 = 2 , 0010 = 2
If the last data of the frame arrives in BDMA Tx Buffer,
the data transfer from the BDMA Tx Buffer to the MAC
TxFIFO starts immediately, regardless of the level of
these bits.
The BDMATXDPTR register must be assigned before this
bit is set.
ETHERNET CONTROLLER
Reset Value
0x00000000
0x00000000
2 12
,....., 11xx = 2
7-15