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HDLC CONTROLLER
Bit
Bit Name
Number
[13:12]
Rx widget alignment
(RxWA)
[14]
DMA Tx stop or skip
(DTxnSTSK)
[15]
DMA Rx stop or skip
(DRxnSTSK)
[16]
DMA Rx memory
address decrement
(DRxMADEC)
[17]
Tx flag idle (TxFLAG)
[18]
Tx single flag
(TxSFLAG)
[19]
Tx loop-back mode
(TxLOOP)
[20]
Rx echo mode
(RxECHO)
[21]
Tx abort extension
(TxABTEXT)
[22]
Tx abort (TxABT)
8-32
Table 8-10. HCON Register Description (Continued)
These bits determine how many bytes are invalid in the first memory
word of the frame to be received. The invalid bytes are inserted when the
word is assembled in the HRXFIFO.
00 = No Invalid byte
10 = 2 invalid bytes
This bit determines a DMA Tx stop or skip when DMA has not the
ownership associated with the Tx buffer descriptor. DMA Tx is disabled in
this condition when this bit is not set.
(0 = Not Owner Tx stop, 1 = Not Owner Tx BD skip)
This bit determines a DMA Rx stop or skip when DMA has not the
ownership associated with the Rx buffer descriptor. If this bit is not set,
DMA Rx is disabled.
(0 = Not Owner Rx stop, 1 = Not Ower Rx BD skip)
This bit determines whether the address is incremented or decremented.
If this bit is set to '1', then the address will be decremented.
This bit selects the flag 'time fill' mode (active idle) or the mark idle mode
(inactive idle) for the transmitter. The selected active or inactive idle state
continues until data is sent (after nRESET has return to High level). The
flag idle pattern is 7EH; the mark idle pattern is FFH.
This bit controls whether separate closing and opening flags are
transmitted in succession to delimit frames. When this bit is '0',
independent opening and closing flags are transmitted in order to
separate frame.
When this bit is set to '1', the closing flag of the current frame serves as
the opening flag of the next frame.
This bit is used for self-testing. If this bit is set to '1', the transmit data
output (TxD) is internally connected to the receiver data input (RxD). In
Loop-back mode, nCTS and nDCD inputs are ignored. For normal
operation, this bit should always be '0'.
Setting this bit to '1' selects the auto-echo mode of operation. In this
mode, the TXD pin is connected to RXD as in local loop-back mode, but
the receiver still monitors the RXD input.
When this bit is set to '1', the abort pattern that is initiated when TxABT =
'1' is extended to at least 16 bits of 1s in succession, and the mark idle
state is entered.
When this bit is set to '1', an abort sequence of at least eight bits of 1s is
transmitted. The abort is initiated and the HTxFIFO is cleared. TxABT is
then cleared automatically by hardware.
Description
01 = 1 invalid byte
11 = 3 invalid bytes
S3C2500B
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