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INSTRUCTION SET
3.30 FORMAT 11: SP-RELATIVE LOAD/STORE
15
14
13
1
0
0
3.30.1 OPERATION
The instructions in this group perform an SP-relative load or store. The THUMB assembler syntax is shown in the
following table.
L
THUMB Assembler
0
STR Rd, [SP, #Imm]
1
LDR Rd, [SP, #Imm]
NOTE: The offset supplied in #Imm is a full 10-bit address, but must always be word-aligned (ie bits 1:0 set to 0),
since the assembler places #Imm >> 2 in the Word8 field.
3.30.2 INSTRUCTION CYCLE TIMES
All instructions in this format have an equivalent ARM instruction as shown in Table 3-18. The instruction cycle
times for the THUMB instruction are identical to that of the equivalent ARM instruction.
Examples
STR
3-84
11
10
12
1
L
Rd
[7:0] Immediate Value
[10:8] Destination Register
[11] Load/Store Bit
0 = Store to memory
1 = Load from memory
Figure 3-40. Format 11
Table 3-18. SP-Relative Load/Store Instructions
ARM Equivalent
STR Rd, [R13 #Imm]
LDR Rd, [R13 #Imm]
R4, [SP,#492]
8
7
Add unsigned offset (255 words, 1020 bytes) in Imm to
the current value of the SP (R7). Store the contents of
Rd at the resulting address.
Add unsigned offset (255 words, 1020 bytes) in Imm to
the current value of the SP (R7). Load the word from the
resulting address into Rd.
; Store the contents of R4 at the address
; formed by adding 492 to SP (R13).
; Note that the THUMB opcode will contain
; 123 as the Word8 value.
Word 8
Action
S3C2500B
0
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