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HDLC CONTROLLER
31
30 29 28 27 26 25
A
R
R
T
T
x
x
R
u
x
t
N
R
R
x
E
E
S
o
O
E
C
V
V
t
o
N
R
C
p
[0] Tx reset (TxRS)
0 = Normal
[1] Rx reset (RxRS)
0 = Normal operation
[2] DMA Tx reset (DTxRS)
0 = Normal operation
[3] DMA Rx reset (DRxRS)
0 = Normal operation
[4] Tx enable (TxEN)
0 = Tx disabled
[5] Rx enable (RxEN)
0 = Rx disabled
[6] DMA Tx enable (DTxEN)
0 = DMA Tx disabled
[7] DMA Rx enable (DRxEN)
0 = DMA Rx disabled
[8] DPLL enable (DPLLEN)
0 = Disable
1 = Enable; DPLL enters search mode for a locking edge in the incoming data stream.
[9] BRG enable (BRGEN)
0 = BRG counter is inbibited.
1 = BRG counter is enabled.
[10] Tx 4 word burst mode (Tx4WD)
0 = 1-word mode selected.
[11] Rx 4 word burst mode (Rx4WD)
0 = 1-word mode selected.
[13:12] Rx widget algnment (RxWA)
00 = No invalid byte
01 = 1 invalid byte
10 = 2 invalid byte
11 = 3 invalid byte
[14] DMA Tx stop or skip (DTxSTSK)
0 = DMA Tx stops when DMA not owner bit is set.
1 = DMA Tx skips when DMA not owner bit is set.
[15] DMA Rx stop or skip (DRxSTSK)
0 = DMA Rx stops when DMA not owner bit is set.
1 = DMA Rx skips when DMA not owner bit is set.
[16] DMA Rx memory address decrement (DRxMADEC)
0 = Address is incremented.
[17] Tx flag idle (TxFLAG)
0 = Enter mark idle mode (a bit pattern of consecutive ones)
1 = Enter time fill mode (a bit pattern of consecutive opening (closing)
flag, as in string 01111110 01111110......
8-34
24
23 22
21
20 19
T
R
T
T
T
R
T
T
x
x
x
x
x
x
x
x
N
D
D
P
A
E
L
A
O
I
T
R
B
B
C
O
C
S
R
M
T
H
O
T
R
C
B
E
O
P
C
O
X
N
T
1 = TxFIFOmand Tx block are reset.
1 = Tx enabled
1 = Rx enabled
1 = DMA Tx enabled
1 = DMA Rx enabled
1 = 4-word mode selected.
1 = 4-word mode selected.
1 = Address is decremented.
Figure 8-14. HDLC Control Register (HCON)
18 17 16
15 14
13 12 11
T
T
D
D
D
R
R
x
x
R
R
T
x
x
S
F
x
x
x
W
4
F
L
M
S
S
A
W
L
A
A
T
T
D
A
G
D
S
S
G
E
K
K
C
1 = RxFIFO and Tx block are reset.
1 = DMA Tx block is reset.
1 = DMA Rx block is reset.
10 9
8 7 6
5
4
3
T
B
D
D
D
R
T
D
x
R
P
R
T
x
x
R
4
G
L
x
x
E
E
x
W
E
L
E
E
N
N
R
D
N
E
N
N
S
N
S3C2500B
2
1
0
D
R
T
T
x
x
x
R
R
R
S
S
S
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