Des/3Des Status Register; Des/3Des Interrupt Enable Register - Samsung S3C2500B User Manual

S3C2500B

11.3.2 DES/3DES STATUS REGISTER

Bit Number
[0] Idle
[3:1] Reserved
[4] Available DESINFIFO
[5] Empty DESINFIFO
[6] Full DESINFIFO
[7] Reserved
[8] Valid DESOUTFIFO
[9] Empty DESOUTFIFO
[10] Full DESOUTFIFO

11.3.3 DES/3DES INTERRUPT ENABLE REGISTER

Bit Number
[0] Int Idle
Reserved
[3:1]
[4] Int Available
DESINFIFO
Reserved
[7:5]
[8] Int Valid DESOUTFIFO
Table 11-3. DES/3DES Status Register Description
Bit Name
This bit indicates whether DES/3DES is running or not
These bits have 0 value.
DESINFIFO is vacant 4(or 2, depends on DESCON[7]) words or
more, this bit is set to 1.
DESINFIFO is vacant all.
DESINFIFO has 8 words valid data. CPU can't write in any more.
This bit has 0 value.
DESOUTFIFO has 4(or 2, depends on DESCON[7]) valid words or
more, this bit is set to 1.
DESOUTFIFO is vacant all.
DESOUTFIFO has 8 words valid data. CPU have to read data
immediately.
Table 11-4. DES/3DES Interrupt Enable Register Description
Bit Name
Interrupt enable register for DES/3DES engine operation
0 = Disable
1 = Interrupt signal is generated when the status register [0] (Idle) bit
goes to high which means the end of the current DES/3DES
operation.
Interrupt enable register for input FIFO, DESINFIFO
0 = Disable
1 = Interrupt signal is generated when the status register [4]
(Available DESINFIFO) bit goes to high.
Interrupt enable register for output FIFO, DESOUTFIFO
0 = Disable
1 = Interrupt signal is generated when the status register [8] (Valid
DESOUTFIFO) bit goes to high.
Description
Description
DES/3DES
11-5