Samsung S3C2500B User Manual page 263

S3C2500B MEMORY CONTROLLER
5.6.3.3 Wait Control Register
Slow external I/O devices requiring a long delay cycles on data read and write, should set EWAITENn in the
WAITCON register. (In this case nEWAIT pin should connected to the external I/O device, if multiple slow
external I/O devices are connected to nEWAIT, each WAIT signals of external I/O devices should be or.)
nEWAIT is low active signal. When nEWAIT is a low, S3C2500B is waiting until nEWAIT is high again.
nREADY in the WAITCON register is used when the external I/O device is ready for transferring data. When
nREADY is low, S3C2500B transfers data.
In addition, Ext I/O controller provides COHDIS in the WAITCON register. When this COHDIS is enabled as '1',
Ext I/O contoller disables chip selection hold time(TCOH) while access the same bank except first access cycle.
So, TCOHDIS helps you to access slow External I/O devices more quickly. Performance by using COHDIS in the
WAITCON register when slow External I/O is used, could be improved. If you use slow External I/O, you must
set TCOH to a proper value because you have to prevent the data collision. But, when you set TCOH to a non-
zero value, all types of data access in the selected bank have TCOH cycle time. So although write to write, read
to read, and write to read access don't have to use TCOH cycle, memory controller extends chip select signal
during TCOH cycle. It decreases the system performance. In S3C2500B, to improve this operation, we add
TCOHDIS field. If you set COHDIS to '1', although TCOH isn't zero, TCOH is ignored in write to write, read to
read, and write to read access. In those case memory controller operates as if TCOH is zero.
Table 5-18. WAIT Control Register
Register Address R/W Description Reset Value
WAITCON 0xF0010024 R/W Wait control register 0x00000000
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