Endian Modes - Samsung S3C2500B User Manual

S3C2500B

5.5 ENDIAN MODES

S3C2500B supports both little-endian and big-endian for external memory or I/O devices by setting the pin BIG.
Below tables(5-3 through 5-14) are show the program/data path between the CPU register and the external
memory using little-/big-endian and word/half-word/byte access.
Table 5-3 and 5-4.
Using big-endian and word access, Program/Data path between register and external memory.
WA=Address whose LSB is 0, 4, 8, C, HA=Address whose LSB is 0, 2, 4, 6, 8, A, C, E
BA=Address whose LSB is 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F
EA=External Address
Table 5-3. External 32-bit Datawidth Store Operation with Big-Endian
Transfer Width
Bit Num.
CPU Register Data
CPU Address
Bit Num.
CPU Data Bus
External Address (ADDR)
Bit Num.
External Data
Timing Sequence
Table 5-4. External 32-bit Datawidth Load Operation with Big-Endian
Transfer Width
Bit Num.
CPU Register Data
CPU Address
Bit Num.
CPU Data Bus
External Address (ADDR)
Bit Num.
External Data
Timing Sequence
X=Don't care
STORE (CPU Reg → → External Memory)
32-bit 16-bit
31 0 31 0
abcd xxab
WA HA
31 0 31 0
abcd abab
31 0 31 0
dcba xxba
LOAD (CPU Reg ← ← External Memory)
32-bit 16-bit
31 0 31 0
abcd xxab
WA HA
31 0 31 0
abcd abab
31 0 31 0
dcba dcba
31 0 31 0
xxcd xxxa
HA+1 BA
31 0 31 0
cdcd aaaa
EA
31 0 31 0
dcxx xxxa
31 0 31 0
xxcd xxxa
HA+1 BA
31 0 31 0
cdcd aaaa
EA
MEMORY CONTROLLER
8-bit
31 0 31 0
xxxb xxxc
BA+1 BA+2
31 0 31 0
bbbb cccc
31 0 31 0
xxbx xcxx
8-bit
31 0 31 0
xxxb xxxc
BA+1 BA+2
31 0 31 0
bbbb cccc
31 0
dcba
31 0
xxxd
BA+3
31 0
dddd
31 0
dxxx
31 0
xxxd
BA+3
31 0
dddd
5-7