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S3C2500B
16.4.4 INTERRUPT OFFSET REGISTER
The interrupt offset registers, INTOFFSET_FIQ and INTOFFSET_IRQ, contain the interrupt offset address of the
interrupt, which has the highest priority among the pending interrupts. The content of the interrupt offset address
is "index value of the interrupt source".
If all interrupt pending bits are "0" when you read this register, the return value is "0x00000027".
This register is valid only under the IRQ or FIQ mode in the ARM940T. In the interrupt service routine, you
should read this register before changing the CPU mode.
If the lowest interrupt priority (priority 0) is pending, the INTOFFSET value will be "0x00000000". The
reset value will, therefore, be changed to "0x00000027" (to be different from interrupt pending priority 0).
Register
INTOFFSET_FIQ
0xF0140018
INTOFFSET_IRQ
0xF014001C
Table 16-6. INTOFFSET_FIQ, INTOFFSET_IRQ Register
Address
R/W
R
R
NOTE
Description
FIQ interrupt offset register
IRQ interrupt offset register
INTERRUPT CONTROLLER
Reset Value
0x00000027
0x00000027
16-9
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