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MEMORY CONTROLLER
5-6
ADDR[23:0]
DATA[31:0]
B0SIZE[1:0]
nRCS[7:0]
nEWAIT/nREADY
S3C2500B
nSDWE/nWE16
nWBE/nBE/DQM[3:0]
nSDCS[1:0]
Figure 5-2. Memory Controller Bus Signals
XBMACK
XBMREQ
nOE
HCLKO
CKE
nSDRAS
nSDCAS
Address & Data
Adjust with pin
selection
ROM & SRAM
Interface signals
External device
interface signals
ROM, SRAM, Flash
and SDRAM common
signals
SDRAM Interface
signals
S3C2500B
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