High-Speed Uart Receive Buffer Register - Samsung S3C2500B User Manual

S3C2500B

14.3.5 HIGH-SPEED UART RECEIVE BUFFER REGISTER

S3C2500B has a 32-byte Receive FIFO, and the bottom of FIFO is HURXBUF. All data to be received are stored
in this register at first in FIFO mode, if next buffer has invalid data, then shifted to next buffer. But in non-FIFO
mode, a new received data will be moved to HURXBUF. The High-Speed UART receive buffer registers,
HURXBUF contain an 8-bit data value to be received over the High-Speed UART channel.
Registers Offset Address
HURXBUF 0xF0070010
0xF0080010
Bit Number
[7:0] Receive data
31
Table 14-11. HURXBUF Registers
R/W
R High-Speed UART receive buffer register
Table 14-12. High-Speed UART Receive Register Description
Bit Name
This field contains the data received over the single channel High-
Speed UART. When the High-Speed UART finishes receiving a
data frame, the receive data ready bit in the High-Speed UART
status register, HUSTAT[14], should be "1". This prevents reading
invalid receive data that may already be present in the HURXBUF.
Whenever the HURXBUF is read, the receive data valid
bit(HUSTAT[14]) is automatically cleared to "0".
[7:0] Receive data for UART
Figure 14-6. High-Speed UART Receive Buffer Register
SERIAL I/O (HIGH-SPEED UART)
Description
Description
8 7
Receive Data
Reset Value
–
0
14-17