Samsung S3C2500B User Manual page 229

S3C2500B
SYSCFG Bit
UPLLFD [25]
PPLLFD [24]
BIG [16]
REMAP [8]
MISALIGN [7]
HCLKO_DIS [4]
ARB [0]
UPLL filter disable
This bit determines whether the USB PLL output is filtered or not
during the configuration. When this bit is set to "0", the USB PLL
output is filtered to be provided to the USB during the configuration.
In this case, the glitch output from PLL can be masked. When this
bit is set to "1", the USB PLL output is not filtered to be provided to
the USB.
PPLL filter disable
This bit determines whether the PHY PLL output is filtered or not
during the configuration. When this bit is set to "0", the PHY PLL
output is filtered to be provided to the PHY during the configuration.
In this case, the glitch output from PLL can be masked. When this
bit is set to "1", the PHY PLL output is not filtered to be provided to
the PHY.
Little / Big endian information (Read only)
0 = Little endian
External memory address remapping enable
0 = Remap disable
ROM Bank0 : 0x00000000
ROM Bank1 : 0x01000000
ROM Bank2 : 0x02000000
ROM Bank3 : 0x03000000
ROM Bank4 : 0x04000000
ROM Bank5 : 0x05000000
ROM Bank6 : 0x06000000
ROM Bank7 : 0x07000000
SDRAM Bank0 : 0x40000000
SDRAM Bank1 : 0x80000000
Misalign Exception Enable
S3C2500B asserts the data abort exception in case of CPU
misaligned accesses. But there is a limitation to that you should set
off Instruction/Data cache when you want misaligned access aborts.
HCLKO output disable
If this bit is set to "1", HCLKO output is activated only when sdram
access - sdram read/write or refresh - is enabled. If this bit is set to
"0", HCLKO is always activated.
0 = Enabled always
System bus arbitration method
0 = Round-robin
Description
1 = Big endian
1 = Remap Enable
ROM Bank0 : 0x80000000
ROM Bank1 : 0x81000000
ROM Bank2 : 0x82000000
ROM Bank3 : 0x83000000
ROM Bank4 : 0x84000000
ROM Bank5 : 0x85000000
ROM Bank6 : 0x86000000
ROM Bank7 : 0x87000000
SDRAM0 bank0 : 0x00000000
SDRAM1 bank1 : 0x40000000
1 = Enabled during sdram access.
1 = Fixed priority
SYSTEM CONFIGURATION
Initial State
0
0
–
0
0
0
0
4-17