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Figure
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S3C2500B RISC MICROCONTROLLER
List of Figures
Read Timing Diagram 1 .........................................................................................5-29
Write Timing Diagram 1 .........................................................................................5-30
Read Timing Diagram 2 .........................................................................................5-31
Write Timing Diagram 2 .........................................................................................5-32
Read after Write at the Same Bank (COHDIS = 1) .................................................5-33
Read Timing Diagram (Muxed Bus)........................................................................5-34
Write Timing Diagram (Muxed Bus) .......................................................................5-35
Write Timing Diagram (nEWAIT)............................................................................5-36
Write Timing Diagram (nREADY) ...........................................................................5-37
SDRAM Configuration Register 0 ...........................................................................5-49
SDRAM Command Register...................................................................................5-51
SDRAM Refresh Timer Register.............................................................................5-52
SDRAM Write Buffer Time-out Register .................................................................5-53
Single Read Operation (CAS Latency=2).................................... 5-54
Single Read Operation (CAS Latency=3).................................... 5-55
Single Write Operation ................................................... 5-56
Burst Read Operation (CAS Latency = 2) ................................... 5-57
Burst Read Operation (CAS Latency = 3) ................................... 5-58
Burst Write Operation.............................................................................................5-59
2
I
C Block Diagram..................................................................................................6-1
Master Transmitter and Slave Receiver..................................................................6-3
Master Receiver and Slave Transmitter..................................................................6-4
Start and Stop Conditions.......................................................................................6-5
Data Transfer Format .............................................................................................6-7
2
I
C Control Status Register.....................................................................................6-10
Ethernet Diagram ...................................................................................................7-1
Data Structure of Tx Buffer Descriptor....................................................................7-10
Data Structure of Rx Buffer Descriptor ...................................................................7-11
Data Structure of the Receive Frame .....................................................................7-12
Fields of an IEEE802.3/Ethernet Frame .................................................................7-38
CSMA/CD Transmit Operation ...............................................................................7-40
Timing for Transmission without Collision...............................................................7-41
Timing for Transmission with Collision in Preamble................................................7-42
Receiving Frame without Error ...............................................................................7-43
Receiving Frame with Error ....................................................................................7-43
CSMA/CD Receive Operation ................................................................................7-44
MAC Control Frame Format ...................................................................................7-46
Timing Relationship of Transmission Signals at MII................................................7-50
Timing Relationship of Reception Signals at MII.....................................................7-50
MDIO Sourced by PHY...........................................................................................7-50
MDIO Sourced by STA ...........................................................................................7-50
(Continued)
Title
Page
Number
xix
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