Samsung S3C2500B User Manual page 285

S3C2500B
31
RESERVED
[0] eXternal data bus Width : XW
0 = external bus width is 32 bit ,1 = external bus width is 16 bit
[1] Auto Pre-charge control for SDRAM accesses: AP
0 = Auto pre-charge ,
[3:2] CAS Latency: CL
00 = Reserved
[5:4] SDRAM device Density of bank 1: D1
00 = 16 Mbit SDRAM memory devices.
01 = 64 Mbit SDRAM memory devices.
10 = 128 Mbit SDRAM memory devices.
11 = 256 Mbit SDRAM memory devices.
[7:6] SDRAM device Density of bank 0: D0
00 = 16 Mbit SDRAM memory devices.
01 = 64 Mbit SDRAM memory devices.
10 = 128 Mbit SDRAM memory devices.
11 = 256 Mbit SDRAM memory devices.
[9:8] Row Pre-charge time: RP
00 = 1 cycle
[11:10] RAS to CAS delay: RCD
00 = 1 cycle
[15:12] Row Cycle: RC
0000 = 1 cycle
0100 = 5 cycles
1000 = 9 cycles
1100 = 13cycles
[19:16] Row Active time: RAS
0000 = 1 cycle
0100 = 5 cycles
1000 = 9 cycles
1100 = 13cycles
[31:20] Reserved
20 19 16
RAS
1 = No auto pre-charge
01 = 1 cycles 10 = 2 cycles
01 = 2 cycles 10 = 3 cycles
01 = 2 cycles 10 = 3 cycles
0001 = 2 cycles 0010 = 3 cycles
0101 = 6 cycles 0110 = 7 cycles
1001 = 10 cycles 1010 = 11 cycle
1101 = 14 cycles 1110 = 15 cycles
0001 = 2 cycles 0010 = 3 cycles
0101 = 6 cycles 0110 = 7 cycles
1001 = 10 cycles 1010 = 11 cycle
1101 = 14 cycles 1110 = 15 cycles
Figure 5-23. SDRAM Configuration Register
15 12 11 10 9 8 7 6
RC RCD RP
11 = 3 cycles
11 = 4 cycles
11 = 4 cycles
0011 = 4 cycles
0111 = 8 cycles
1011 = 12 cycles
1111 = 16 cycles
0011 = 4 cycles
0111 = 8 cycles
1011 = 12 cycles
1111 = 16 cycles
MEMORY CONTROLLER
5 4 3 2 1 0
A X
D0 D1 CL
P W
5-49