Samsung S3C2500B User Manual page 48

PRODUCT OVERVIEW
Group Pin Name
System CLKMOD [1:0]
Config
(20)
CPU_FREQ [2:0]
BUS_FREQ [2:0]
nRESET
TMODE
BIG
1-14
Table 1-1. S3C2500B Signal Descriptions (Continue)
Pin Type Pad Type
2 I
3 I
3 I
1 I
1 I
1 I
Phic The CLKMOD pin determines internal clock
scheme of S3C2500B. When CLKMOD is "00",
the nfast clock mode is defined. In this mode,
the same clock is used as CPU clock and
system clock. When CLKMOD is "11", the
async clock mode is defined. In this mode, the
CPU clock and system clock can operate
independently as long as the CPU clock is
faster than system clock.
phic CPU Clock Frequency Selection.
phic System Bus Clock Frequency Selection.
phis Not Reset. NRESET is the global reset input
for the S3C2500B and nRESET must be held
to "low" for at least 64 clock cycles for digital
filtering.
phicd Test Mode. The TMODE pin setting is
interpreted as follows:
0 = normal operating mode
1 = chip test mode.
phicd BIG endian mode select pin
When this pin state is "0", the S3C2500B
operates in litte endian mode. When this pin
state is "1", the S3C2500B operates in big
endian mode.
S3C2500B
Description