Samsung S3C2500B User Manual page 338

ETHERNET CONTROLLER
7.4.2.5 MAC Transmit Status Register
A transmission status flag is set in the transmit status register, MACTXSTAT, whenever the corresponding event
occurs. In addition, an interrupt is generated if the corresponding enable bit in the transmit control register is set.
A MAC TxFIFO parity error sets TxParErr, and also clears MTxEn, if the interrupt is enabled.
Registers Address
MACTXSTATA 0xF00B000C
MACTXSTATB 0xF00D000C
Bit Number
[7:0]
[11:8] Transmission collision count
(MCollCnt)
[12] Transmission deferred
(MTxDefer)
[13] Signal quality error (SQEErr)
[14] Transmission halted
(MTxHalted)
[15] Paused (MPaused)
[31:16] Reserved
7-28
Table 7-34. MACTXSTAT Register
R/W
R/W
R/W
Table 7-35. MAC Transmit Status Register Description
Bit Name
– These bits are equivalent to the BMTXSTAT.7-0
This 4-bit value is the count of collisions that occurred while
successfully transmitting the frame.
This bit is set if transmission of a frame was deferred because
of a delay during transmission.
According to the IEEE802.3 specification, the SQE signal
reports the status of the PMA (MAU or transceiver) operation
to the MAC layer. After transmission is complete and 1.6 ms
has elapsed, a collision detection signal is issued for 1.5 ms to
the MAC layer. This signal is called the SQE test signal. The
MAC sets this bit if this signal is not reported within the IFG
time of 6.4ms.
This bit is set if the MTxEn bit is cleared or the MHaltImm bit
is set
This bit is set if transmission of frame was delayed due to a
Pause being received.
Not applicable.
Description
Transmit status
Transmit status
Description
S3C2500B
Reset Value
0x00000000
0x00000000