Samsung S3C2500B User Manual page 393

S3C2500B
Bit Bit Name
Number
[23] Tx preamble (TxPRMB)
[24] Tx data terminal ready
(TxDTR)
[25] Rx frame discontinue
(RxDISCON)
[26] Tx no CRC (TxNOCRC)
[27] Rx no CRC (RxNOCRC) When this bit is set to '1', the receiver does not check for CRC by
[28] Auto enable (AutoEN)
[29] Transparent Rx stop
(TRxSTOP)
[30] Transmit reverse
(TxREV)
[31] Receive reverse
(RxREV)
Table 8-10. HCON Register Description (Continued)
When this bit is set to '1', the content of the HPRMB register is
transmitted as many TxPL bit values in interrupt mode instead of mark
idle or time fill mode. This is useful for sending the data needed by the
DPLL to lock the phase. It is used only by the Transmitter Interrupt Mode,
not by theTransmitter DMA Mode. (see 8-14)
The TxDTR bit directly controls the nDTR output state. Setting this bit
forces the nDTR pin to Low level. When you clear the TxDTR bit, nDTR
goes High.
When this bit is set, the frame currently received is ignored and the data
in this frame is discarded. Only the last frame received is affected. There
is no effect on subsequent frames, even if the next frame enters the
receiver when the discontinue bit is set. This bit is automatically cleared
after a cycle.
When this bit is set to '1', the CRC is not appended to the end of a frame
by hardware. It is used only by the Transmitter Interrupt Mode, not by the
Transmitter DMA Mode. (see 8-14)
hardware. (CRC data is always moved to the HRXFIFO.)
This bit programs the function of both nDCD and nCTS. However, TxEN
and RxEN must be set before the nCTS and nDCD pins can be used.
When this bit is '0', if the nCTS becomes high, the transmitter sends mark
idle pattern. However, though the nDCD becomes high, the receiver can
receive the data.
When this bit is '1', if the nCTS becomes high, the transmitter send mark
idle but clears the HTxFIFO and the Tx block. If nDCD becomes high, the
receiver can't operate, and the HRXFIFO and Rx blocks are cleared.
This bit reset value is zero. If this bit set to one, the receive operation is
ended in transparent mode. And then the receiver start to search Sync. If
this bit set to one in HDLC mode, RxFIFO cleared except for receiver.
So, the data in receiver can be moved to Rx FIFO at this time.
If this bit set to one, the data will be sent MSB first. If this bit set to zero,
LSB first.
If this bit set to one, the received data will be MSB first. If this bit set to
zero, LSB first.
Description
HDLC CONTROLLER
8-33