Gdma Programmable Priority Registers - Samsung S3C2500B User Manual

GDMA CONTROLLER

12.3.1 GDMA PROGRAMMABLE PRIORITY REGISTERS

The GDMA can support the fixed priority and the round-robin priority for the local arbitration of six GDMA
channels by register setting. Especially, the GDMA can program the priority order in the fixed priority mode as
well as the ratio of the bus occupancy in the round-robin priority mode.
The local priority of six channels of GDMA can be programmed by the fixed priority or the round-robin priority in
similar manner to the AHB bus priority. Please refer to Chapter 4, The System Configuration.
The GDMA programmable priority registers are DPRIC (Programmable Priority Register for Configuration),
DPRIF (Programmable Priority Register for Fixed) and DPRIR (Programmable Priority Register for Round-
Robin).
If the GDMA priority configuration register (0xF0051000) DPRIC = 0x1, the programmable fixed priority is run by
DPRIF register. Each GDMA channel has its own fixed priority index. For example, the GDMA channel 0 has the
index 0. The reset value of DPRIF register is 0x00543210. The first field of DPRIF[3:0] indicates the highest
priority. So, the GDMA channel 0 has the highest priority in local arbitration when DPRIC = 0x1 and the DPRIF
has the reset value. For example, DPRIC = 0x1 and the DPRIF is 0x00431520, the fixed priority order from the
highest to the lowest is GDMA channel 0, channel 2, channel 5, channel 1, channel 3, and channel 4.
If the GDMA priority configuration register (0xF0051000) DPRIC = 0x0, the programmable round-robin priority is
run by DPRIR register. All GDMA channels own their respective field position in DPRIR. The ratio of the bus
occupancy can be programmed by writing an arbitrary value on each field. The arbitrary value can be from 0x0 to
0xF. The ratio of the bus occupancy of the GDMA channel in the first field is
(dprir0+1)/((dprir5+1)+(dprir4+1)+(dprir3+1)+(dprir2+1)+(dprir1+1)+(dprir0+1)). The reset value of DPRIR register
is 0x0. So each GDMA channel has the same bus occupancy ratio when DPRIC = 0x0 and the DPRIR has the
reset value. For example, DPRIC = 0x0 and the DPRIR is 0x20F100, the expected ratios of the bus occupancy of
the GDMA channel 0, channel 1, channel 2, channel 3, channel 4, and channel 5 are 1/24, 1/24, 2/24, 16/24,
1/24, and 3/24, respectively.
Register Address
DPRIC 0xF0051000
DPRIF 0xF0052000
DPRIR 0xF0053000
12-4
Table 12-2. GDMA Programmable Priority Registers
R/W
R/W GDMA priority configuration register
R/W GDMA programmable priority register for fixed
R/W GDMA programmable priority register for round-
robin
Description
S3C2500B
Reset Value
0x00000000
0x00543210
0x00000000