Samsung S3C2500B User Manual page 481

S3C2500B
Bit Number Bit Name
[12] In mode, AuTo
SET (IATSET)
[14:13] Reserved
[15] CSR2 SETtable
(CSR2SET)
[16] Out mode, Out
packet ReaDY
(OORDY)
[17] Out mode, Fifo
FULL (OFFULL)
[18] Out mode, fifo
OVER run
(OOVER)
[19] Out mode, Data
ERRor (ODERR)
[20] Out mode,
Fifo FLUSH
(OFFLUSH)
Table 10-24. USBEP4CSR Register Description (Continued)
MCU
R/W
W
R/C
R
R
R
R/W
USB
This bit is only valid only when endpoint 4 is set to
IN.
If set, whenever the MCU writes MAXP data,
IINRDY will be automatically be set without any
intervention from MCU.
If the MCU writes less than MAXP data, then
IINRDY bit has to be set by the MCU.
Default = 0
– 0 = USBEP4CSR[12:8] isn't overwritten when MCU
writes a 32bit value to USBEP4CSR register.
1 = USBEP4CSR[12:8] is overwritten.
S This bit is valid only when endpoint 4 is set to OUT.
The USB sets this bit once it has loaded a packet of
data into the FIFO. Once the MCU reads the FIFO
for the entire packet, this bit should be cleared by
MCU
R/W This bit is valid only when endpoint 4 is set to OUT.
Indicates no more packets can be accepted
if USBEP4CSR[17:16] is
00 = No packet in FIFO
01 = 1 packet in FIFO
11 = 2 packet of MAXP =< 1/2 FIFO size or
1 packet of MAXP > FIFO size
R/W This bit is valid only when endpoint 4 is set to OUT
ISO.
This bit is set if the core is not able to load an OUT
ISO packet into the FIFO
R/W This bit is valid only when endpoint 4 is set to OUT
ISO
This bit should be sampled with OORDY
When set, it indicates the data packet due to be
unloaded by the MCU has an error (either bit
stuffing or CRC). If two packets are loaded into the
FIFO, and the second packet has an error, then this
bit gets set only after the first packet is unloaded.
This is automatically cleared when OORDY gets
cleared.
C This bit is valid only when endpoint 4 is set to OUT.
The MCU writes a "1" to flush the FIFO.
This bit can be set only when OORDY is set. The
packet due to be unloaded by the MCU will be
flushed.
USB CONTROLLER
Description
10-41