Interrupt Mask Registers - Samsung S3C2500B User Manual

S3C2500B
31 30 29 28
EXTMOD
[6:0] External interrupt mode bits
NOTE:

16.4.2 INTERRUPT MASK REGISTERS

The interrupt mask registers, INTMASK and EXTMASK, contain interrupt mask bits for each interrupt source.
Register Address
INTMASK 0xF0140008
EXTMASK 0xF014000C
27 26 25 23 22 21 20
24
Each of the 7 bits in the external interrupt mode enable register, EXTMOD,
corresponds to an external interrupt source. When the source interrupt
mode bit is set to 1, the interrupt is processed by the ARM940T core
in FIQ (fast interrupt) mode. Otherwise, it is processed in IRQ mode
(normal interrupt). The 7 external interrupt sources are mapped as follows:
[6] IOM2 interrupt
(0 = IRQ interrupt mode, 1 = FIQ interrupt mode )
[5] EXT 5 interrupt
[4] EXT 4 interrupt
[3] EXT 3 interrupt
[2] EXT 2 interrupt
[1] EXT 1 interrupt
[0] EXT 0 interrupt
Figure 16-2. External Interrupt Mode Register (EXTMOD)
Table 16-4. INTMASK, EXTMASK Register
R/W
R/W Internal Interrupt mask register
R/W External Interrupt mask register
19 18 17 16 15 14 13 12
Description
INTERRUPT CONTROLLER
11 10 9 8 7 6 5 4
X X X
3 2 1 0
X X X X
Reset Value
0xFFFFFFFF
0x8000007F
16-5