Hdlc Interrupt Enable Register - Samsung S3C2500B User Manual

HDLC CONTROLLER
8.7.5 HDLC INTERRUPT ENABLE REGISTER (HINTEN)
Registers
HINTENA 0×F010000C
HINTENB 0×F011000C
HINTENC 0×F012000C
Bit Bit Name
Number
[3:0] Reserved
[4] TxFCIE
[5] TxFAIE
[6] Reserved
[7] TxSCTSIE
[8] TxUIE
[9] RxFAIE
[10] TxFGIE
[11] RxFDIE
[12] Reserved
[13] RxSDCDIE
[14] RxFVIE
[15] RxIDLEIE
[16] RxABTIE
[17] RxCRCEIE
[18] RxNOIE
[19] RxOVIE
[20] Reserved
[21] Reserved
[22] DTxABTIE
[23] RxIERRIE
[24] DRxFDIE
[25] Reserved
[26] DRxNOIE
[27] DTxFDIE
[28] Reserved
[29] DTxNOIE
[30] DPLLOMIE
[31] DPLLTMIE
8-42
Table 8-13. HINTENA, HINTENB, and HINTENC Register
Address R/W
R/W
R/W
R/W
Table 8-14. HINTEN Register Description
Tx frame complete interrupt enable
Tx FIFO available to write interrupt enable
CTS transition has occurred interrupt enable
Tx under-run has occurred interrupt enable
Rx FIFO available to read interrupt enable
Tx Frame Good interrupt enable
Rx flag detected interrupt enable
DCD transition interrupt enable
Rx frame valid interrupt enable
Idle detected interrupt enable
Abort detected interrupt enable
CRC error frame interrupt enable
Non-octet aligned frame interrupt enable
Rx overrun interrupt enable
DMA Tx abort interrupt enable
Rx internal error interrupt enable
DMA Rx frame done interrupt enable
DMA Rx not owner interrupt enable
DMA Tx frame done every transmitted frame interrupt enable
DMA Tx not owner interrupt enable
DPLL one clock missing interrupt enable
DPLL two clocks missing interrupt enable
Description

HDLC Interrupt Enable Register

HDLC Interrupt Enable Register
HDLC Interrupt Enable Register
Description
Reset Value
0X00000000
0X00000000
0X00000000
–
–
–
–
–
–
–
S3C2500B