Samsung S3C2500B User Manual page 562

S3C2500B
Table 14-6. High-Speed UART Status Register Description (Continued)
Bit Number
[12] Receive Event time out
(E_RxTO)
[13] AutoBaud Rate
Detection (AUBDDN)
[14] Data Set ready (DSR)
[15] Clear To Send (CTS)
[16] CTS Event occurred
(E_CTS)
[17] Transmitter Idle (TI)
[18] Transmit Holding
Register Empty (THE)
[19] Transmit FIFO Empty
(TFEMT)
[20] Transmit FIFO full
(TFFUL)
[31:21] Reserved
Bit Name
During Receive FIFO mode, if there is a valid data in URXFIFO or
Receive FIFO within a promised time internal which is determined
according to WL(Word Length) , this bit is set to '1' . URXFIFO is for
non-FIFO mode and Receive FIFO is for FIFO mode.
If the E_RxTO interrupt enable bit, HUINT[12], is "1", an interrupt is
generated when a receive event time out is detected and valid data
reside in HURXBUF or Receive FIFO. You can clear this bit by
writing '1' to this bit.
NOTE: Event time = WL*4 +12
This bit is automatically set to "1" when high-speed UART finishes
AutoBaud Rate Detection procedure. You can clear this bit by
writing "1" to this bit.
This bit is only for CPU to monitor High-Speed UART.
When HUnDSR0/HUnDSR1 level is low, this bit is set. And
HUnDSR0/ HUnDSR1 high, this bit is cleared.
This bit is only for CPU to monitor High-Speed UART.
When HUnCTS0/ HUnCTS1 level is low , this bit is set. And
HUnCTS0/ HUnCTS1 high, this bit is cleared.
This bit is set to '1' whenever HUnCTS0/ HUnCTS1 level changed.
If the E_CTS interrupt enable bit, HUINT[16], is "1", a interrupt is
generated when a CTS event is occurred.
You can clear this bit by writing '1' to this bit.
HUSTAT[17] is automatically set to '1' when the transmit holding
register has no valid data to transmit and when the TX shift register
is empty. The reset value is '1'
In Transmit FIFO mode, when Transmit FIFO is empty to trigger
level, this bit set to '1'.
In non-FIFO mode, when HUTXBUF is empty without regarding Tx
shift register , this bit set to '1'.
An interrupt or DMA request is generated when HUSTAT[18] is "1".
In case of HUCON[1:0]='01' and HUINT[18]=1, an interrupt
requested, and HUCON[1:0]='10' or '11', DMA request occurred.
You can clear this bit by writing TxDATA into HUTXBUF or Transmit
FIFO.
This bit is only for CPU to monitor High-Speed UART.
When Transmit FIFO is empty, this bit is set to '1'.
After reset, default value is '1'
This bit is only for CPU to monitor High-Speed UART.
When Transmit FIFO is full, this bit is set to '1'.
After reset, default value is '0' .
Not applicable.
Description
This bit set to one when the Rx data resides in RxFIFO.
SERIAL I/O (HIGH-SPEED UART)
14-11