Samsung S3C2500B User Manual page 86

PROGRAMMER' ' S MODEL
2.7.2 The THUMB State Register Set
The THUMB state register set is a subset of the ARM state set. The programmer has direct access to eight
general registers, R0–R7, as well as the Program Counter (PC), a stack pointer register (SP), a link register (LR),
and the CPSR. There are banked stack pointers, link registers and Saved Process Status Registers (SPSRs) for
each privileged mode. This is shown in Figure 2-4.
System & User
R0
R1
R2
R3
R4
R5
R6
R7
SP
LR
PC
CPSR
= banked register
2-6
THUMB State General Registers and Program Counter
FIQ Supervisor
R0 R0
R1 R1
R2 R2
R3 R3
R4 R4
R5 R5
R6 R6
R7 R7
SP_fiq SP_svg
LR_fiq LR_svc
PC PC
THUMB State Program Status Registers
CPSR CPSR
SPSR_fiq SPSR_svc
Figure 2-4. Register Organization in THUMB State
About IRQ
R0 R0
R1 R1
R2 R2
R3 R3
R4 R4
R5 R5
R6 R6
R7 R7
SP_abt SP_irq
LR_abt LR_irq
PC PC
CPSR CPSR
SPSR_abt SPSR_irq
S3C2500B
Undefined
R0
R1
R2
R3
R4
R5
R6
R7
SP_und
LR_und
PC
CPSR
SPSR_und