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S3C2500B
Table 13-5. Console UART Status Register Description (Continued)
Bit Number
[4]
Overrun Error (OER)
[5]
Control Character Detect
(CCD)
[10:6]
Reserved
[11]
Receiver in idle
(RXIDLE)
[16:12]
Reserved
[17]
Transmitter Idle (TI)
[18]
Transmit Holding
Register Empty (THE)
[31:19]
Reserved
Bit Name
This bit is automatically set to '1' whenever an overrun error occurs
during a serial data receiving operation. When CURXBUF has a
previous valid data and a new received data is going to be written
into CURXBUF, CUSTAT[4] is set to '1'.
If the OER interrupt enable bit, CUINT[4], is '1', a interrupt is
generated when a overrun error occurs.
You have to clear this bit by writing '1' to this bit. If not, UART may
be stopped.
CUSTAT[5] is automatically set to '1' to indicate that a control
character has been received.
If the CCD interrupt enable bit, CUINT[5], is '1', an interrupt is
generated when a control character is detected.
You can clear this bit by writing '1' to this bit.
NOTE: Software flow control mode does not affects Tx/Rx operation
This bit is only for CPU to monitor the receiver state of console
UART. The RXIDLE status bit indicates inactive state of
CURXBUF.
CUSTAT[17] is automatically set to '1' when the transmit holding
register has no valid data to transmit and when the TX shift register
is empty. The reset value is '1'
When CUTXBUF is empty without regarding TX shift register , this
bit set to '1'.
An interrupt is generated when CUSTAT[18] is '1', CUCON[1:0] is
'01', and CUINT[18] is '1'.
You can clear this bit by writing some data into CUTXBUF.
Description
this bit. This bit informs only whether UART receives control
character or not. Namely, if user want to stop Tx/Rx operation.
User must program that routine.
SERIAL I/O (CONSOLE UART)
13-9
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