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S3C2500B
31
B
S
[0] Run enable (RE)
0 = Disable GDMA operation
[3:1] Mode selection (MODE)
000 = Software mode (Memory to Memory, or Momory to/from USB)
001 = External Request mode (for external devices)
010 = HUART TX mode (HUART from memory)
011 = HUART RX mode (HUART to memory)
100 = DES IN mode (DES from memory)
101 = DES OUT mode (DES to memory)
110, 111 = Reserved
[4] Single/block mode (SB)
0 = One xGDMA_Req initiates a single GDMA operation
1 = One xGDMA_Req initiates a whole GDMA operation
[5] Four-data burst enable (FB)
0 = Disable 4-data burst mode
1 = Enable 4-data burst mode
[7:6] Transfer size (TS)
00 = Byte (8-bit)
10 = Word (32-bit)
[9:8] Source address direction (SD)
00 = Increase source address
01 = Decrease source address
10 = Do not change source address (fixed)
11 = Reserved
[11:10] Destination address direction (DD)
00 = Increase destination address
01 = Decrease destination address
10 = Do not change destination address (fixed)
11 = Reserved
[12] Interrupt enable (IE)
0 = Do not generate a interrupt when GDMA completes
1 = Generate a interrupt when GDMA completes successfully
[16:13] External GDMA ACK cycle count (XCNT)
0000 = 1 cycle
0100 = 5 cycles
1000 = 9 cycles
1100 = 13 cycles
[31] Busy status (BS)
0 = GDMA is idle
17
RESERVED
0001 = 2 cycles
0101 = 6 cycles
1001 = 10 cycles
1101 = 14 cycles
Figure 12-3. GDMA Control Register
16
13 12 11 10 9 8 7 6 5 4 3
X
I
D
C
E
D
N
T
1 = Enable GDMA operation
01 = Half-word (16-bit)
11 = No use
0010 = 3 cycles
0110 = 7 cycles
1010 = 11 cycles
1110 = 15 cycles
1 = GDMA is active
GDMA CONTROLLER
M
S
T
F
S
O
D
S
B
B
D
E
0011 = 4 cycles
0111 = 8 cycles
1011 = 12 cycles
1111 = 16 cycles
1 0
R
E
12-11
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