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MEMORY CONTROLLER
31
Reserved
[31:24] Reserved
[23] TCOH disable for bank 7: COHDIS7
This forces TCOH to '0' for read to read, write to write, and write to read access in the bank 7
0 = disable
[22] TCOH disable for bank 6: COHDIS6
[21] TCOH disable for bank 5: COHDIS5
[20] TCOH disable for bank 4: COHDIS4
[19] TCOH disable for bank 3: COHDIS3
[18] TCOH disable for bank 2: COHDIS2
[17] TCOH disable for bank 1: COHDIS1
[16] TCOH disable for bank 0: COHDIS0
[15] External wait enable for bank 7: EWAITEN7
0 = disable
[14] External wait enable for bank 6: EWAITEN6
[13] External wait enable for bank 5: EWAITEN5
[12] External wait enable for bank 4: EWAITEN4
[11] External wait enable for bank 3: EWAITEN3
[10] External wait enable for bank 2: EWAITEN2
[9] External wait enable for bank 1: EWAITEN1
[8] External wait enable for bank 0: EWAITEN0
[7] nWait / nReady select for bank 7: NREADY7
0 = nWait
[6] nWait / nReady select for bank 6: NREADY6
[5] nWait / nReady select for bank 5: NREADY5
[4] nWait / nReady select for bank 4: NREADY4
[3] nWait / nReady select for bank 3: NREADY3
[2] nWait / nReady select for bank 2: NREADY2
[1] nWait / nReady select for bank 1: NREADY1
[0] nWait / nReady select for bank 0: NREADY0
5-28
24
23
22
21 20
19
C
C
C
C
C
O
O
O
O
O
H
H
H
H
H
D
D
D
D
D
I
I
I
I
I
S
S
S
S
S
7
6
5
4
3
1 = enable
1 = enable
1 = nReady
Figure 5-13. Wait Control (WAITCON) Register Configuration
18
17
16
15
14
13
12
11
E
E
E
E
E
C
C
C
W
W
W
W
W
O
O
O
A
A
A
A
A
H
H
H
I
I
I
I
I
D
D
D
T
T
T
T
T
I
I
I
E
E
E
E
E
S
S
S
N
N
N
N
N
2
1
0
7
6
5
4
3
10
9
8
7
6 5
4
3
E
E
E
N
N
N
N
N
W
W
W
R
R
R
R
R
A
A
A
E
E
E
E
E
I
I
I
A
A
A
A
A
T
T
T
D
D
D
D
D
E
E
E
Y
Y
Y
Y
Y
N
N
N
7
6
5
4
3
2
1
0
S3C2500B
2
1
0
N
N
N
R
R
R
E
E
E
A
A
A
D
D
D
Y
Y
Y
2
1
0
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