Clock Control Register - Samsung S3C2500B User Manual

S3C2500B
4.9.3 CLOCK CONTROL REGISTER (CLKCON)
There is a clock control register(CLKCON) in system configuration. For the purpose of power save, Clock control
register(CLKCON) can be programmed at low frequency and the slower clock than the system clock can be made
by clock dividing value . When the internal system clock is divided by CLKCON, its duty-cycle is changed. If
CLKCON is programmed to zero, the internal system clock remains the same as the internal clock. In other case,
the duty cycle of internal system clock is no logner 50%.
Register Address
CLKCON 0xF0000008
CLKCON Bit
Reserved [31:16]
DVAL [15:0]
HCLK
HCLK
CLKCON = 0
HCLK
CLKCON = 1
HCLK
CLKCON = 2
R/W
R/W
Reserved
System clock dividing value.
If all bits are 0, non-divided clock is used.
Only one bit can be set in CLKCON[15:0]. That is, the clock dividing
value is defined as 1, 2, 4, 8, 16, ...
Internal system clock is (PLL output clock) / (CLKCON+1).
Figure 4-7. Divided System Clock Timing Diagram
Description

Clock control register

Description
SYSTEM CONFIGURATION
Reset Value
0x00000000
Initial State
0
0
4-19