Samsung S3C2500B User Manual page 561

SERIAL I/O (HIGH-SPEED UART)
Table 14-6. High-Speed UART Status Register Description (Continued)
Bit Number
[4] Overrun Error (OER)
[5] Control Character Detect
(CCD)
[6] Data carrier Detect Lost
(DCDL)
[7] Receive FIFO Data
trigger level reach
(RFREA)
[8] Receive FIFO empty
(RFEMT)
[9] Receive FIFO full
(RFFUL)
[10] Receive FIFO overrun
(RFOV)
[11] Receiver in idle (RIDLE)
14-10
Bit Name
This bit automatically set to "1" whenever an overrun error occurs
during a serial data receiving operation. When HURXBUF has a
previous valid data, but a new received data is going to be written
into HURXBUF during non-FIFO mode and when a new received
data is going to be written into RXFIFO with FIFO full during FIFO
mode. HUSTAT[4] is set to '1'.
If the OER interrupt enable bit, HUINT[4], is "1", a interrupt is
generated when a overrun error occurs.
You have to clear this bit by writing '1' to this bit. If not, UART may
be stopped.
HUSTAT[5] is automatically set to "1" to indicate that a control
character has been received.
If the CCD interrupt enable bit, HUINT[5], is "1", an interrupt is
generated when a control character is detected.
You can clear this bit by writing '1' to this bit.
NOTE: Software flow control mode does not affects Tx/Rx operation this
This bit set to 1, if HUnDCD0/HUnDCD1 pin is high at the time High-
Speed UART Receiver checks a newly received data whether the
data is good frame or not.
If the DCD interrupt enable bit, HUINT[6], is "1", a interrupt is
generated when a data carrier is detected.
This bit can be used for error check bit in hardware flow control
mode.
In Receive FIFO mode, this bit indicate Receive FIFO has valid data
and reach Rx trigger level. So High-Speed UART request DMA to
move data in Receive FIFO. In non-FIFO mode, if HURXBUF has a
received data , this bit is set to '1' also,
An interrupt or DMA request is generated when HUSTAT[7] is "1". In
case of HUCON[3:2]='01' and HUINT[7]=1,interrupt requested, and
HUCON[3:2]='10' or '11', DMA request occurred.
You can clear this bit by reading Receive FIFO or HURXBUF with a
good data. If any error, this bit is cleared by writing '1' to
corresponding error bit in HUSTAT register.
This bit is only for CPU to monitor High-Speed UART. When Receive
FIFO is empty, this bit is set to '1'. After reset, default value is '1' .
This bit is only for CPU to monitor High-Speed UART. When Receive
FIFO is full, this bit is set to '1'. After reset, default value is '0'
This bit is set to '1' when Receive FIFO overrun occurs during the
Receive FIFO mode.
You can clear this bit by writing '1' to this bit.
This bit is only for CPU to monitor the receiver state of High-Speed
UART. The RxIDLE status bit indicates that the inactive state of
RxDATA.
Description
bit. This bit informs only whether UART receives control character
or not. Namely, if user want to stop Tx/Rx operation. User must
program that routine.
S3C2500B