The Mac Receiver Block - Samsung S3C2500B User Manual

ETHERNET CONTROLLER S3C2500B

7.3.5 THE MAC RECEIVER BLOCK

It complies with the IEEE802.3 standard for carrier sense multiple access with collision detection (CSMA/CD)
protocol.
After it receives a frame, the receiver block checks for a number of error conditions: CRC errors, alignment
errors, and length errors. By setting bits in appropriate control registers some error condition is disabled.
Depending on the CAM status, the destination address and the receiver block may reject an otherwise
acceptable frame.
7.3.5.1 MAC RxFIFO (MRxFIFO)
The MRxFIFO accepts data one byte at a time. The parity starts with the destination address. The receiver
updates the counter with the number of bytes received. As the FIFO stores the data, the CAM block checks the
destination address against its stored address. If the CAM recognizes the address, the MRxFIFO continues
receiving the frame. If the CAM block does not recognize the address and rejects the frame, the receiver block
discards the frame and flushes the MRxFIFO.
7.3.5.2 CAM and Address Recognition
The CAM compares the destination address of the received frame to stored addresses. If it finds a match, the
receive state machine continues to receive the frame. The CAM is organized to hold six-byte address entries.
The CAM can store 21 address entries.
The CAM address entries 0, 1, and 18 are used to send the pause control frame. To send a pause control frame,
you must write the destination address to CAM0, the source address to CAM1, and length/type, op-code, and
operand to the CAM18 entry. You must write the MAC transmit control register to set the send pause control bit.
In addition, CAM19 and CAM20 can be used to construct a user-define control frame.
7.3.5.3 Parallel CRC Checker
The receiver block computes a CRC across the data and the transmitted CRC, and then checks that the resulting
syndrome is valid. A parallel CRC checking scheme handles data arriving in 4-bit nibbles at 100M-bps. To
support full-duplex operation, the receiver and transmitter blocks have independent CRC circuits.
7.3.5.4 Receive State Machine
In MII mode, the receiver block receives data from the MII on the RXD[3:0] lines. This data is synchronized to
RX_CLK at 25 MHz or 2.5MHz. In 7-wire mode, and at 10MHz, data is received on the RXD_10M line only.
After it detects the preamble and SFD, the receive state machine arranges data in byte configurations, generates
parity, and stores the result in the MRxFIFO one byte at a time. If the CAM block accepts the destination
address, the MRxFIFO stores the rest of the frame. Any error in reception will reset the MRxFIFO and the state
machine will wait for the end of the current frame. It will then be idle while it is waiting for the next preamble and
SFD.
7.3.5.5 BDMA Interface Receive State Machine
The BDMA I/F receive state machine issues the Rx_rdy signal whenever data is present in the receive FIFO. The
last byte of the packet is signaled by asserting the Rx_EOF.
In case there are any errors during the reception, or if there is a CRC error at the end, the BDMA I/F receive
state machine asserts the Rx_toss signal to indicate that the received packet should be discarded.
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