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2
I
C CONTROLLER
SDA by
Transmitter
SDA by
Receiver
SCL from
Master
S
Start
Condition
Even in this case, the master IC generates the timing and terminates the transfer.
The master IC is always responsible for generating the clock signals on the I
can only be altered by 1) a slow slave IC which "stretches" the signal by temporarily holding the clock line Low, or
2) by another master IC during arbitration.
6.4.2 GENERAL CHARACTERISTICS
Both SDA and SCL are bi-directional lines which are connected to a positive supply voltage through a pull-up
resistor.
2
When the I
C is free, the SDA and SCL lines are both high level. The output stages of I
to the bus have an open-drain or open-collector to perform the wired-AND function. Data on the I
transferred at a rate up to 100K-bits/s. The number of interfaces that can be connected to the bus is solely
dependent on the limiting bus capacitance of 400 pF.
6.4.3 BIT TRANSFERS
Due to the variety of different ICs (CMOS, NMOS, and I2L, for example) which can be connected to the I
levels of logic zero (low) and logic one (high) are not fixed and depend on the associated level of V
pulse is generated for each data bit that is transferred.
6-4
Acknowledge
from receiver
MSB
8
1
2
R/W
Address
Figure 6-3. Master Receiver and Slave Transmitter
Acknowledge from
transmitter
MSB
9
1
2
ACK
Data
8
9
ACK
2
C. Bus clock signals from a master
2
C interfaces connected
2
C can be
DD
S3C2500B
P
Stop
Condition
2
C, the
. One clock
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