Peripheral Clock Disable Register - Samsung S3C2500B User Manual

SYSTEM CONFIGURATION
4.9.4 PERIPHERAL CLOCK DISABLE REGISTER (PCLKDIS)
There is a peripheral clock disable register in system configuration. You can set this register with the specific
value for the purpose of power save. If you set PCLKDIS[0] to "1", the clock for GDMA channel 0 is
disabled. Similarly, you control the clock input of each peripheral.
Register Address
PCLKDIS 0xF000000C
PCLKDIS Bit
SRreq [31]
SRack [30]
Reserved [29:28]
IOM2 [27]
HDLC2 [26]
HDLC1 [25]
HDLC0 [24]
SDRAMC [23]
MEMCON [22]
DES [21]
IIC [20]
IOPC [19]
WDT [18]
TIMER5 [17]
TIMER4 [16]
TIMER3 [15]
TIMER2 [14]
TIMER1 [13]
TIMER0 [12]
HUART1 [11]
HUART0 [10]
CUART [9]
USB [8]
ETHERC1 [7]
ETHERC0 [6]
GDMA5 [5]
GDMA4 [4]
GDMA3 [3]
GDMA2 [2]
GDMA1 [1]
GDMA0 [0]
4-20
R/W
R/W
SDRAM Self-refresh request
SDRAM Self-refresh acknowledge ( Read only)
Reserved for future use
IOM2 clock disable
HDLC2 clock disable
HDLC1 clock disable
HDLC0 clock disable
SDRAMC clock disable
MEMCON clock disable
DES clock disable
IIC clock disable
IOPC clock disable
Watch dog timer clock disable
TIMER5 clock disable
TIMER4 clock disable
TIMER3 clock disable
TIMER2 clock disable
TIMER1 clock disable
TIMER0 clock disable
HUART clock disable
HUART clock disable
CUART clock disable
USB clock disable
ETHERC1 clock disable
ETHERC0 clock disable
GDMA channel 5 clock disable
GDMA channel 4 clock disable
GDMA channel 3 clock disable
GDMA channel 2 clock disable
GDMA channel 1 clock disable
GDMA channel 0 clock disable
Description

Peripheral clock disable register

Description
S3C2500B
Reset Value
0x00000000
Initial State
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0