Samsung S3C2500B User Manual page 337

S3C2500B
7.4.2.4 MAC Transmit Control Register
Registers Address
MACTXCONA 0xF00B0008
MACTXCONB 0xF00D0008
Bit Number
[0] Transmit enable (MTxEn)
[1] Transmit halt request
(MTxHalt)
[2] Suppress padding (MNoPad)
[3] Suppress CRC (MNoCRC)
[4] Fast back-off (MFBack)
[5] No defer (MNoDef)
[6] Send Pause (MSdPause)
[7] MII 10M-b/s SQE test mode
enable (MSQEn)
[31:8] Reserved
Table 7-32. MACTXCON Register
R/W
R/W
R/W
Table 7-33. MAC Transmit Control Register Description
Bit Name
Set this bit to enable transmission. To stop transmission
immediately, clear the transmit enable bit to '0'.
Set this bit to halt the transmission after completing the
transmission of any current frame.
Set this bit not to generate pad bytes for frames of less than
64 bytes.
Set this bit to suppress addition of a CRC at the end of a
frame.
Set this bit to use faster back-off times for testing.
Set this bit to disable the defer counter. (The defer counter
keeps counting until the carrier sense (CrS) bit is turned off.)
Set this bit to send a pause command or other MAC control
frame. The send pause bit is automatically cleared when a
complete MAC control frame has been transmitted. Writing a
'0' to this register bit has no effect.
Set this bit to enable MII 10M-b/s SQE test mode.
Not applicable.
Description
Transmit control
Transmit control
Description
ETHERNET CONTROLLER
Reset Value
0x00000000
0x00000000
7-27