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6.1 Overview ...........................................................................................................................................6-1
6.2 Features ............................................................................................................................................6-1
6.3 Functional Description .......................................................................................................................6-2
2
C Concepts .....................................................................................................................................6-3
6.4.1 Basic Operation ......................................................................................................................6-3
6.4.2 General Characteristics ..........................................................................................................6-4
6.4.3 Bit Transfers ...........................................................................................................................6-4
6.4.4 Data Validity ...........................................................................................................................6-5
6.4.5 Start And Stop Conditions.......................................................................................................6-5
6.4.6 Data Trsansfer Operations......................................................................................................6-6
2
C Special Registers .........................................................................................................................6-9
6.5.1 Control Status Register...........................................................................................................6-9
6.5.2 Shift Buffer Register ...............................................................................................................6-11
6.5.3 Prescaler Register ..................................................................................................................6-11
6.5.4 Prescaler Counter Register.....................................................................................................6-12
6.5.5 Interrupt Pending Register ......................................................................................................6-12
7.1 Overview ...........................................................................................................................................7-1
7.2 Features ............................................................................................................................................7-2
7.3 MAC Function Blocks.........................................................................................................................7-3
7.3.1 Media Independent Interface (MII) ..........................................................................................7-3
7.3.2 Physical Layer Entity (PHY)....................................................................................................7-4
7.3.3 Buffered Dma Interface (BDI) .................................................................................................7-4
7.3.4 The MAC Transmitter Block....................................................................................................7-4
7.3.5 The MAC Receiver Block........................................................................................................7-6
7.3.6 Flow Control Block..................................................................................................................7-7
7.3.7 Buffered DMA (BDMA) Overview ...........................................................................................7-7
7.4 Ethernet Controller Special Registers.................................................................................................7-13
7.4.1 BDMA Relative Special Register ............................................................................................7-15
7.4.2 MAC Relative Special Register...............................................................................................7-24
7.5 Ethernet Operations...........................................................................................................................7-37
7.5.1 MAC Frame Format................................................................................................................7-37
7.5.2 The MII Station Manager ........................................................................................................7-45
7.5.3 Full-Duplex Pause Operations ................................................................................................7-46
7.5.4 Error Signalling.......................................................................................................................7-48
7.5.5 Timing Parameters for MII Transactions .................................................................................7-50
S3C2500B RISC MICROCONTROLLER
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